1. Field of the Invention
The present invention relates a Large Scale Integrated (hereinafter referred to as LSI) layout and a method for fabrication of the same.
2. Description of the Prior Art
In the fabrication of semiconductor integrated circuits, it is necessary to use a plurality of fabrication masks such as a diffusion pattern forming mask and an interconnection pattern forming mask. Usually, these masks are changed depending upon the kind or type of semiconductor integrated circuits and the production of masks are troublesome. In general, therefore, it is not preferable to manufacture many different kinds of semiconductor integrated circuits in small amounts for the respective kinds of circuits.
However, a request for the manufacture of various semiconductor integrated circuits, whose kinds or types are different depending upon user's requirements and whose amounts of production are relatively small, is customary. Therefore, "master slice" methods have been proposed. In a typical master slice method, the same mask is used at least until the diffusion step for every kind of semiconductor circuits but different interconnection patterns are employed for the respective kinds. Namely, only the interconnection pattern forming mask is changed.
A problem arises in to the case where the master slice method is applied to the change of an LSI layout to a different kind, which layout includes insulated gate metal-oxide-semiconductor transistors of enhancement type and insulated gate metal-oxide-semiconductor transistors (hereinafter referred to as MOSFET) of the depletion type. For a circuit section such as a read only memory (ROM), its logic or circuit function is changed depending upon which MOSFETs arranged usually in a matrix form should be provided as depletion type MOSFETs. On the other hand, for a logic function section other than a ROM, its logic function is changed by the change of an interconnection pattern forming mask. When the simultaneous change of both the logic functions is desired, both of the depletion type MOSFET forming mask and the interconnection pattern forming mask must be changed.